Course Description: Modern digital design practices
based on Hardware Description Languages Verilog, VHDL) and CAD tools,
particularly logic synthesis. Emphasis on design practice and the
underlying algorithms. Introduction to deep submicron design issues,
particularly interconnect and low power, and to modern applications,
including multimedia, wireless, telecommunications and computing. Students
must have access to a Verilog simulator and design synthesis tools (e.g.
Synopsys Design Compiler and Synopsys Design Analyzer) in order to be able
to take this course.
Course Objectives: The objective of this course is to
prepare you to be an ASIC or FPGA designer in industry. To this end we
will focus on how to execute and capture a large complex design in an HDL,
using Verilog as the main example. We will also cover a number of other
issues important to ASIC designers, including Verification, Design For
Test, low power design, etc. You will demonstrate your ability to design a
complex ASIC or FPGA function via a major project.
Course Outline by Topical Areas:
| Introduction to ASIC Design
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| Introduction To Design with Verilog
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| How to Design Complex Systems
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